1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more particularly to a deep depletion mode dynamic random access memory (DRAM) cell and a method of making the DRAM cell utilizing spacer technology.
2. Description of the Related Art
Processes for forming dynamic random access memory (DRAM) circuits are complex and expensive. There are a plurality of conventional cell concepts typically employed. For example, the deep trench DRAM cell and the stacked DRAM cell are typically utilized, both of which store a specific amount of charge representing a predetermined logic state (e.g., a typical minimum charge is 30 fF/cell).
The charge is transferred by the transfer gate or word line and then is detected on bit lines and amplified.
An example of a conventional structure is shown in FIG. 3. More particularly, a semiconductor layer 32 is formed on a substrate 31. An insulating layer 33 is formed on the semiconductor layer 32.
A diffused layer 34 is formed at one end of the layer 33 and an electrode 35 of an information storage capacitor is provided at another end of the layer 34 opposed to the location of the region 34, thereby forming a capacitor 30. An interlayer insulating film 36 is formed to cover the electrode 35 of the capacitor 30. On upper surfaces of insulating film 36 and the insulating layer 33, a word line 37 in read-out and a gate electrode 38 of a metal oxide semiconductor field-effect transistor (MOSFET) are integrally formed, except on that portion of the layer 33 which corresponds to the diffused region 34.
The capacitor 30 has a constant voltage Vc applied thereto, while the electrical charge is transferred to the capacitor 30 upon conductance of the MOSFET. Then, an inversion layer or a deep depletion state is brought about at the surface of the semiconductor layer 32 in the capacitor 30 so that the width of a space charge layer may be controlled and a high speed operation may be achieved.
However, the above-mentioned conventional device has several significant drawbacks. First, such a device is constructed using conventional lithography techniques and thus the pitch is relatively large. Further, packing density is relatively low.
Another problem of the conventional DRAM structures is that conventional DRAM cells cannot be made smaller as a "state of the art" deep trench or stacked capacitor cell, which is approximately 0.5 .mu.m.sup.2 for a quarter micron technology.
Further, while the process for such a cell is made much simpler than for a conventional trench cell, the circuits for reading and writing of a dynamic memory cell are usually much more complex since there is an additional storage line (SL).
Thus, the conventional DRAM cell cannot be made smaller than a capacitor cell, and thus a dynamic memory cell results, which despite its simpler fabrication process, has no sufficient advantage compared to the well-established trench and stacked capacitor technologies.